You will work with and lead a team of engineers designing IPs for advanced broadband communications SOCs. These chips integrate complete PHY and MAC layers (including broadband RF/analog circuits, digital ASIC, and CPU subsystems) on a single die, and are being designed in deep-submicron CMOS processes for use in next-generation wireless, optical, and wireline systems.
You will provide your team with critical leadership in architecture, design, debug and production ramp of these products. Working within a mid-sized company environment will offer you oversight of the entire product development cycle, while fully challenging your ability to mentor and lead the team developing complex analog & mixed signal solutions for 5G wireless and high speed wire-line markets, and collaborating closely with other engineering teams to make the overall product successful.
We are looking for an engineering leader with analog/mixed-signal design and product experience. You should have a track record of innovation and an interest in working in a dynamic and fast-paced environment along with the desire to recruit, mentor and lead talented engineers.
- Strong background in analog-mixed circuit design and circuit analysis
- Working knowledge of integration of analog IPs into SOCs, including verification
- Experience recruiting and mentoring junior and experienced engineers
- Broad technical knowledge with the ability to learn quickly
- Masters’ in Electrical Engineering with 15 years of experience; Ph.D. preferred with 12 years of experience